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Atlanta chip startup Nagare Labs exited stealth with a $5M pre-seed led by Playground Global to build Z2RAM, a memory tier aimed at AI accelerators.
Key Takeaways
- Nagare Labs raised a $5M pre-seed round led by Playground Global; valuation and other investors are undisclosed.
- Z2RAM is a capacitor-less, transistor-based memory aimed at a tier between on-chip SRAM and HBM.
- The technology is still a laboratory prototype, with scale-up and reliability validation ahead.
Lead
Nagare Labs, a Georgia Tech spinout based in Atlanta, announced its emergence from stealth on October 26, 2026, alongside a $5 million pre-seed round led by Playground Global. The company is developing Z2RAM, a memory architecture that pairs SRAM-like access speed with DRAM-level bit density. Former Intel CEO Pat Gelsinger, a general partner at Playground Global, joins the board as a director.
The round is small by semiconductor standards, where a single test chip run can cost a large share of $5M. Nagare did not disclose a valuation, headcount, or any additional investors.
What Is Z2RAM and How Does It Work?
Z2RAM is a capacitor-less memory built from transistors, using oxide-semiconductor devices and standard back-end-of-line fabrication steps. Nagare says the design stacks in three dimensions, with a single lithography exposure per layer and no need for EUV lithography. That claim bears on cost, since bit cost in stacked memory depends heavily on how many patterning steps each layer needs.
The company positions Z2RAM as a new tier between on-chip SRAM and high-bandwidth memory (HBM). Target workloads include AI inference, model weight storage, and key-value cache operations. The architecture is also meant for 3D heterogeneous integration on top of a logic die.
Nagare says it avoids the exotic materials and unfamiliar reliability physics that stalled earlier attempts at new memory types. It relies on fab-compatible materials, tools, and chemicals. Whether that holds at production volumes is untested.
Why Does AI Hardware Need a New Memory Tier?
AI accelerators are limited by memory as much as by compute, because logic scaling has outpaced memory scaling for years. Co-founder Suman Datta described the problem as "the so-called memory wall for modern AI workloads." SRAM is fast but takes up a lot of die area per bit, while DRAM and HBM are denser but slower and sit off the compute die.
A tier that offers more capacity than SRAM at lower latency than HBM would, in principle, keep more model data close to the processor. Inference is the clearest case, where key-value caches grow with context length and weights must be fetched repeatedly. Nagare is betting that this gap is wide enough to support a new product category.
Who Is Behind Nagare Labs?
Datta, the CEO, is a Pettit Chair Professor at Georgia Tech and a co-inventor of Intel's High-k/Metal Gate and Tri-gate transistor architectures. He is the 2026 recipient of the IEEE Andrew S. Grove Award. Co-founder Shimeng Yu is a Dean's Professor at Georgia Tech, the creator of the open-source NeuroSim simulator, and a 2025 SRC Technical Excellence Award recipient.
Both founders hold their academic posts, which gives the company access to university research infrastructure. The terms of the technology license from Georgia Tech were not disclosed.
Gelsinger said in the announcement that Nagare "brings together world-class technical leadership and a brilliant architectural design that operates on existing fab infrastructure."
What Does the Round Imply?
A $5M pre-seed from a lead investor with a hardware focus signals a bet on a team and a technical thesis rather than on a product. There is no prior round to compare against, and no valuation to benchmark. Playground Global has backed deep-technology companies with long development cycles, which fits a company that has yet to leave the lab.
The money likely covers prototype refinement, not manufacturing. The company said it is seeking research and manufacturing partners to move beyond the capacity of university cleanrooms. That search is the main near-term constraint, since fab access for novel memory devices is limited and foundries prioritize volume customers.
What Comes Next for Nagare Labs?
The next milestones are partner agreements, fabricated demonstrations outside the university cleanroom, and reliability data. Memory technologies tend to fail on endurance, retention, and yield rather than on peak speed, so those results will matter more than the architecture itself. A larger seed or Series A would probably depend on them.
The competitive field is crowded. HBM suppliers are expanding capacity and roadmaps, and several emerging memory types have spent years chasing the same gap. Nagare's compatibility with existing fab flows is its clearest argument for being different.
Outlook
Nagare Labs enters the market with a credible founding team, a well-known board member, and a $5M pre-seed that funds early work and little more. Z2RAM addresses a real bottleneck, but it remains a lab prototype with manufacturing scale-up and reliability validation still ahead. Securing fab partners and publishing reliability data in the coming quarters will show whether the architecture can leave the university cleanroom.
