Pomegra
Georgia Tech spinout Nagare Labs emerged from stealth on Oct. 26, 2026 with a $5M seed round led by Playground Global, aiming to cut the cost of moving data in AI chips.
Key Takeaways
- Nagare Labs raised a $5M seed round led by Playground Global; valuation and other investors are undisclosed.
- Its Z2RAM design targets SRAM-class speed at DRAM-class density, still at lab-prototype stage.
- Working memory tiles are targeted within four years, with production shipments within 10.
Lead
Nagare Labs, an Atlanta-based spinout of the Georgia Institute of Technology, emerged from stealth on October 26, 2026 with $5M in seed funding led by Playground Global. The company is developing Z2RAM, a capacitor-less, transistor-based memory that layers directly on top of a logic die. Co-founders Suman Datta and Shimeng Yu, both Georgia Tech professors, say the design addresses the gap between processor speed and memory throughput that limits AI inference. Pat Gelsinger, the former Intel CEO and a Playground general partner, sits on Nagare's board. The company did not disclose a valuation or name other participants.
What Is Z2RAM and How Does It Work?
Z2RAM is a memory architecture that stores data in transistors alone, with no capacitors, and stacks multiple memory layers above the compute die. The channels use oxide semiconductors, which the company says cut off-state leakage by orders of magnitude and allow fast, non-destructive reads.
The first design carries six deposited memory layers on a single die. Nagare projects it could deliver five times the bit density of two-nanometer high-density SRAM. The company says the process runs on standard 300mm back-end-of-line steps, needs no node shrink and does not require EUV lithography.
The pitch is a middle path. SRAM is fast but consumes expensive die area and scales poorly. DRAM and high-bandwidth memory offer capacity, but they sit off-chip and carry latency, energy and thermal costs. Nagare wants to place dense memory on the accelerator itself, removing the interposer hop.
Why Is the Memory Wall Such a Problem for AI?
Compute performance has grown about 70% a year for three decades, while memory bandwidth has grown about 20%, according to the company. That gap leaves processors idle while they wait for data, a constraint that bites hardest in generative AI inference, where model weights and caches are read constantly.
The industry's current answer is HBM, stacked DRAM placed beside the processor. It works, but it is supply-constrained, power-hungry and hard to cool. Any technology that moves meaningful capacity onto the logic die would change that equation, which explains why memory startups attract attention even at the seed stage.
Who Is Behind Nagare Labs?
Datta is a Pettit Chair Professor at Georgia Tech and a co-inventor of Intel's high-k/metal gate and tri-gate transistor architectures. He received the 2026 IEEE Andrew S. Grove Award. Yu is a Dean's Professor at Georgia Tech, created the NeuroSim simulator for compute-in-memory research, and won the 2025 SRC Technical Excellence Award.
Gelsinger said in the announcement that next-generation AI requires "fundamentally rethinking hardware from the memory layer up," and noted the design operates on existing fab infrastructure. Datta framed the problem directly: memory performance has lagged logic scaling, creating the memory wall.
What Does a $5M Seed Buy in Semiconductors?
A $5M seed buys lab work, not silicon at scale. Chip startups usually need far more capital once they move from prototype to foundry runs, and Nagare is still seeking a fabrication partner. Reaching working memory tiles will likely require follow-on rounds many times this size.
The timeline reflects that distance. Nagare aims to sample working tiles within four years of the announcement and ship production parts within 10. For a company founded in 2026, that is a decade-long bet, which fits a deep-tech investor willing to hold through multiple funding cycles but offers little near-term revenue.
Skeptical Read
The performance claims remain unverified. The company has published no third-party validation, and the five-times density figure is a projection for a design that exists as a lab prototype. Oxide-semiconductor transistors have been studied for years, and the distance between a university demonstration and a yield-controlled process at a commercial fab is long.
Incumbents also have a head start. DRAM makers and foundries are advancing HBM and 3D integration on their own schedules, and a new memory cell needs a manufacturing partner willing to qualify it. Gelsinger's presence on the board helps with introductions to that world but does not guarantee a partner.
What Comes Next for Nagare Labs?
The next milestone is a fabrication partner, followed by sample tiles within four years. Along the way, Nagare will need independent measurements of speed, endurance and leakage to support its density claims. A larger Series A would likely follow once a foundry relationship is in place.
Success would put a new option beside SRAM and HBM for AI accelerator designers. Failure would be unremarkable by seed-stage standards, since most memory technologies that reach the lab never reach volume production.
Outlook
Nagare Labs enters the market with credentialed founders, a notable backer and a clear technical target, but with unproven silicon and a long road to revenue. The $5M seed funds the first proof points, and the fabrication partner announcement will be the first real test of whether Z2RAM can leave the lab.
